1. Field of the Invention
The present invention relates to a coupling coefficient measuring method and a coupling coefficient measuring apparatus for a semiconductor memory, and more specifically, it relates to a coupling coefficient measuring method and a coupling coefficient measuring apparatus for a nonvolatile semiconductor memory such as a flash memory.
2. Description of the Prior Art
A nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) is recently watched with interest as a semiconductor memory capable of substituting for a hard disk and a floppy disk, which are magnetic memories.
A memory cell of an EPROM or an EEPROM stores carriers in a floating gate electrode for storing data in response to presence/absence of the carriers and reading data by detecting change of a threshold voltage responsive to presence/absence of the carriers. In particular, the EEPROM includes a flash EEPROM erasing data in the overall memory cell array or dividing the memory cell array into arbitrary blocks for erasing data in units of the blocks. The flash EEPROM is also referred to as a flash memory. The flash memory, capable of increasing the capacity, reducing the power consumption and increasing the speed and excellent in impact resistance, is used in various portable apparatuses. Each memory cell of the flash memory is formed by a single transistor, to advantageously enable easier integration as compared with an EEPROM.
In general, stacked gate and split gate memory cells are proposed for forming such a flash memory.
The stacked gate memory cell injects electrons stored in a channel of a semiconductor substrate into a floating gate electrode as hot electrons in a write operation of storing electrons in the floating gate electrode. At this time, a voltage of 10-odd V must be applied to a control gate electrode. In the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current) is fed from a source or drain region to the floating gate electrode in an erase operation of extracting electrons stored in the floating gate electrode. At this time, a voltage of 10-odd V must be applied between the source or drain region and the floating gate electrode.
The split gate memory cell injects electrons stored in a channel of a semiconductor substrate into a floating gate electrode as hot electrons in a write operation of storing electrons in the floating gate electrode. At this time, a voltage of 10-odd V must be applied to a drain region. In the split gate memory cell, an F-N tunnel current is fed from a control gate electrode to the floating gate electrode in an erase operation of extracting electrons stored in the floating gate electrode. At this time, a voltage of 10-odd V must be applied to the control gate electrode.
Thus, each of the conventional stacked gate and split gate memory cells utilizes hot electrons for injecting electrons into the floating gate electrode in the write operation while utilizing the F-N tunnel current for extracting the electrons stored in the floating gate electrode in the write operation.
In the flash memory, the coupling coefficient between the floating gate electrode and the source region and that between the floating gate electrode and the control gate electrode are important parameters. These coupling coefficients decide controllability in erasing, writing and reading.
In order to control the potential of a floating gate electrode with the minimum voltage (power) in a general split gate flash memory controlling the potential of the floating gate electrode by electrostatic coupling from a source region, the coupling ratio between the source region (source diffusion layer) and the floating gate electrode must be sufficiently large. In this case, it is important to optimize cell creation conditions by correctly measuring the coupling ratio in the stage of development.
In general, the coupling ratio between the floating gate electrode and the control gate electrode is measured through a non-floating gate electrode (NFG) having a test structure. More specifically, a voltage is directly applied to the non-floating gate electrode whose voltage can be controlled by an external power source for measuring a subthreshold current, while the voltage of a control gate electrode is increased in an actual cell for measuring a subthreshold current. The ratio of inclinations (S values) of these subthreshold currents is calculated thereby measuring the coupling coefficient between the floating gate electrode and the control gate electrode. As to the split gate flash memory related to the present invention, it is recognized that the magnitude of coupling between elements other than xe2x80x9ca source and a control gatexe2x80x9d and a floating gate is extremely small. Therefore, the coupling ratio between the floating gate electrode and the source region important in writing is calculated by subtracting the coupling coefficient between the floating gate electrode and the control gate electrode from 1.
In the aforementioned method of measuring the coupling coefficient with the test structure including the non-floating gate electrode, however, it is difficult to independently form an external wire connected to the non-floating gate electrode following refinement of the cell, disadvantageously leading to difficulty in formation of the test structure. Following refinement of the cell, further, the shape of the actual cell may differ from that of the cell of the test structure due to the external wire for the non-floating gate electrode. In this case, the measured value of the subthreshold current in the test structure may differ from that in the actual cell. Consequently, it is difficult to correctly measure the coupling coefficient.
Even if the test structure can be created, there is a possibility of extracting a false value unless measuring conditions are optimized. Thus, the measuring conditions must be carefully set.
An object of the present invention is to provide a coupling coefficient measuring method for a semiconductor memory capable of directly measuring a coupling coefficient in an actual cell without employing a specific test structure including a non-floating gate structure or the like.
Another object of the present invention is to provide a coupling coefficient measuring method for a semiconductor memory capable of correctly measuring a coupling coefficient.
Still another object of the present invention is to provide a coupling coefficient measuring apparatus for a semiconductor memory capable of directly measuring a coupling coefficient in an actual cell without employing a specific test structure including a non-floating gate structure or the like.
According to a first aspect of the present invention, a coupling coefficient measuring method for a semiconductor memory having a first gate electrode and a source region coupled at a prescribed electrostatic coupling ratio comprises steps of increasing a source voltage while setting a drain voltage to a first drain voltage defining a reference value for measuring a first subthreshold current flowing through a first transistor having the first gate electrode as a gate, increasing the source voltage while setting the drain voltage to a second drain voltage higher by a prescribed value than the first drain voltage for measuring a second subthreshold current flowing through the first transistor, reading a first source voltage corresponding to a first value of the first subthreshold current and. a second source voltage corresponding to a second value of the second subthreshold current equal to the first value and calculating the ratio of the difference between the first drain voltage and the second drain voltage to the difference between the first source voltage and the second source voltage thereby obtaining the coupling coefficient between the first gate electrode and the source region.
The coupling coefficient measuring method according to the first aspect changes the drain voltage and increases the source voltage thereby measuring the first and second subthreshold currents and thereafter reads the first source voltage corresponding to the first value of the first subthreshold current and the second source voltage corresponding to the second value of the second subthreshold current equal to the first value while calculating the ratio of the difference between the first and second drain voltages to the difference between the first and second source voltages, whereby the coupling coefficient between the first gate electrode and the source region can be directly obtained in an actual cell without providing a specific test structure including a non-floating gate structure or the like, dissimilarly to the prior art.
In the aforementioned coupling coefficient measuring method for a semiconductor memory according to the first aspect, each of the steps of measuring the first subthreshold current and the second subthreshold current preferably includes steps of keeping the first transistor having the first gate electrode as the gate in an off state while a second transistor having a second gate electrode as a gate is on and thereafter increasing the source voltage thereby increasing the potential of the first gate electrode for turning on the first transistor while the second transistor is sufficiently on and measuring the first subthreshold current or the second subthreshold current flowing through the first transistor. Thus, when keeping the first transistor in an off state while the second transistor is on and thereafter increasing the potential of the first gate electrode for turning on the first transistor while the second transistor is sufficiently on and measuring the first or second subthreshold current, the second transistor is sufficiently on in measurement of the first and second subthreshold currents, whereby the characteristics of the second transistor can be prevented from influencing the first and second subthreshold currents.
In the aforementioned case, the step of keeping the first transistor in an off state while the second transistor is on preferably includes a step of injecting electrons into the first gate electrode thereby increasing the threshold voltage of the first transistor. According to this structure, the first transistor can be readily set off while the second transistor is on.
In the aforementioned case, the second gate voltage is preferably sufficiently higher than the threshold voltage of the second transistor when the first transistor is turned on. According to this structure, the second transistor is sufficiently on before the first transistor is turned on, whereby the characteristics of the second transistor can be effectively prevented from influencing the subthreshold current characteristics of the first transistor.
In the aforementioned case, each of the steps of measuring the first subthreshold current and the second subthreshold current preferably includes a step of increasing a voltage applied to the second gate electrode thereby previously measuring the voltage of the second gate electrode when the first transistor is turned on. According to this structure, the previously measured voltage of the second gate electrode may be simply applied when measuring the first and second subthreshold currents while values of voltages applied to elements other than the second gate electrode and the range of changing the voltages can be kept substantially constant even if the degree of increase of the threshold voltage of the first transistor is dispersed, whereby the measuring operation can be smoothly performed.
In the aforementioned coupling coefficient measuring method for a semiconductor memory according to the first aspect, the steps of measuring the first subthreshold current and measuring the second subthreshold current are preferably carried out while setting potential difference between the source voltage and the first drain voltage or the second drain voltage to allow no writing in the first gate electrode. According to this structure, no writing is performed in the first gate electrode when measuring the first and second subthreshold currents, whereby the measured values of the first and second subthreshold currents can be prevented from changing due to new writing. In this case, the potential difference between the source voltage and the first drain voltage or the second drain voltage is preferably not more than 3 V.
In the aforementioned coupling coefficient measuring method for a semiconductor memory according to the first aspect, the semiconductor memory may include a split gate flash memory.
According to a second aspect of the present invention, a coupling coefficient measuring method for a semiconductor memory having a first gate electrode and a second gate electrode coupled at a prescribed electrostatic coupling ratio comprises steps of increasing a voltage applied to the second gate electrode while setting a voltage applied to a source/drain region to a first voltage defining a reference value for measuring a first subthreshold current flowing through a first transistor having the first gate electrode as a gate, increasing the voltage applied to the second gate electrode while setting the voltage applied to the source/drain region to a second voltage higher by a prescribed value than the first voltage for measuring a second subthreshold current flowing through the first transistor, reading a third voltage of the second gate electrode corresponding to a first value of the first subthreshold current and a fourth voltage of the second gate electrode corresponding to a second value of the second subthreshold current equal to the first value and calculating the ratio of the difference between the first voltage and the second voltage of the source/drain region to the difference between the third voltage and the fourth voltage of the second gate electrode thereby obtaining the coupling coefficient between the first gate electrode and the second gate electrode.
The coupling coefficient measuring method for a semiconductor memory according to the second aspect changes the voltage applied to the source/drain region and increases the voltage of the second gate electrode thereby measuring the first and second subthreshold currents and thereafter reads the third voltage of the second gate electrode corresponding to the first value of the first subthreshold current and the fourth voltage of the second gate electrode corresponding to the second value of the second subthreshold current equal to the first value while calculating the ratio of the difference between the first voltage and the second voltage applied to the source/drain region to the difference between the third voltage and the fourth voltage of the second gate electrode, whereby the coupling coefficient between the first and second gate electrodes can be directly obtained in an actual cell without providing a specific test structure including a non-floating gate structure or the like, dissimilarly to the prior art.
In the aforementioned coupling coefficient measuring method for a semiconductor memory according to the second aspect, the semiconductor memory may include a stacked gate flash memory.
According to a third aspect of the present invention, a coupling coefficient measuring method for a semiconductor memory having a first gate electrode and a second gate electrode coupled at a prescribed electrostatic coupling ratio with the first gate electrode and the second gate electrode serially arranged between a source region and a drain region comprises steps of setting the maximum voltage of the second gate electrode smaller than a voltage obtained by adding the threshold voltage of a second transistor having the second gate electrode as a gate and a drain voltage in a data area employed as a correct measured value when applying a prescribed voltage to the second gate voltage in a prescribed memory cell thereby applying a voltage to the first gate electrode by electrostatic coupling and measuring a first subthreshold current between the source region and the drain region, directly applying a voltage to a test gate electrode in a test memory cell for measuring a second subthreshold current between the source region and the drain region and calculating the ratio between inclination of the first subthreshold current and inclination of the second subthreshold current thereby obtaining the coupling coefficient between the first gate electrode and the second gate electrode.
The coupling coefficient measuring method for a semiconductor memory according to the third aspect sets the maximum voltage of the second gate electrode smaller than the voltage obtained by adding the threshold voltage of the second transistor having the second gate electrode as the gate and the drain voltage when measuring the first subthreshold current in a prescribed actual memory cell as hereinabove described, whereby the drain region of the second transistor can be prevented from supplying electrons to the drain of the first transistor having the first gate electrode as the gate. Therefore, the drain of the first transistor is held in sufficiently low electron concentration. Thus, the first subthreshold current flowing through the first transistor can be measured substantially in a range reflecting only fluctuation of electron concentration on the source of the first transistor. Consequently, the subthreshold current characteristics of only the first transistor can be correctly evaluated. The coupling coefficient between the first and second gate electrodes can be correctly obtained by calculating the ratio between the inclination of the first subthreshold current measured in such a manner and inclination of the second subthreshold current measured by directly applying a voltage to the test gate electrode.
In the aforementioned coupling coefficient measuring method for a semiconductor memory according to the third aspect, the step of measuring the second subthreshold current in the test memory cell preferably includes a step of setting the maximum voltage of the second gate electrode smaller than a voltage obtained by adding the threshold voltage of the second transistor and the drain voltage when measuring the second subthreshold current in the test memory cell. According to this structure, the drain region of the second transistor can be prevented from supplying electrons to the drain of the first transistor in the test memory cell. Therefore, the drain of the first transistor is held in sufficiently low electron concentration. Thus, the first subthreshold current flowing through the first transistor can be measured substantially in a range reflecting only fluctuation of the electron concentration on the source of the first transistor. Consequently, the subthreshold current characteristics of only the first transistor can be correctly evaluated, whereby the second subthreshold current can be correctly measured.
In the aforementioned coupling coefficient measuring method for a semiconductor memory according to the third aspect, the test gate electrode may include a non-floating gate electrode. Further, the semiconductor memory may include a split gate flash memory.
According to a fourth aspect of the present invention, a coupling coefficient measuring apparatus for a semiconductor memory having a first gate electrode and a source region coupled at: a prescribed electrostatic coupling ratio comprises means increasing a source voltage while setting a drain voltage to a first drain voltage defining a reference value for measuring a first subthreshold current flowing through a first transistor having the first gate electrode as a gate, means increasing the source voltage while setting the drain voltage to a second drain voltage higher by a prescribed value than the first drain voltage for measuring a second subthreshold current flowing through the first transistor, means reading a first source voltage corresponding to a first value of the first subthreshold current and a second source voltage corresponding to a second value of the second subthreshold current equal to the first value, and means calculating the ratio of the difference between the first drain voltage and the second drain voltage to the difference between the first source voltage and the second source voltage thereby obtaining the coupling coefficient between the first gate electrode and the source region.
The coupling coefficient measuring apparatus for a semiconductor memory according to the fourth aspect changes the drain voltage and increases the source voltage thereby measuring the first and second subthreshold currents and thereafter reads the first source voltage corresponding to the first value of the first subthreshold current and the second source voltage corresponding to the second value of the second subthreshold current equal to the first value while calculating the ratio of the difference between the first and second drain voltages to the difference between the first and second source voltages, whereby the coupling coefficient between the first gate electrode and the source region can be directly obtained in an actual cell without providing a specific test structure including a non-floating gate structure or the like, dissimilarly to the prior art.
According to a fifth aspect of the present invention, a coupling coefficient measuring apparatus for a semiconductor memory having a first gate electrode and a second gate electrode coupled at a prescribed electrostatic coupling ratio comprises means increasing a voltage applied to the second gate electrode while setting a voltage applied to a source/drain region to a first voltage defining a reference value for measuring a first subthreshold current flowing through a first transistor having the first gate electrode as a gate, means increasing the voltage applied to the second gate electrode while setting the voltage applied to the source/drain region to a second voltage higher by a prescribed value than the first voltage for measuring a second subthreshold current flowing through the first transistor, means reading a third voltage of the second gate electrode corresponding to a first value of the first subthreshold current and a fourth voltage of the second gate electrode corresponding to a second value of the second subthreshold current equal to the first value, and means calculating the ratio of the difference between the first voltage and the second voltage of the source/drain region to the difference between the third voltage and the fourth voltage of the second gate electrode thereby obtaining the coupling coefficient between the first gate electrode and the second gate electrode.
The coupling coefficient measuring apparatus for a semiconductor memory according to the fifth aspect changes the voltage applied to the source/drain region and increases the voltage of the second gate electrode thereby measuring the first and second subthreshold currents and thereafter reads the third voltage of the second gate electrode corresponding to the first value of the first subthreshold current and the fourth voltage of the second gate electrode corresponding to the second value of the second subthreshold current equal to the first value while calculating the ratio of the difference between the first voltage and the second voltage of the source/drain region to the difference between the third voltage and the fourth voltage of the second gate electrode, whereby the coupling coefficient between the first and second gate electrodes can be obtained in an actual cell without providing a specific test structure including a non-floating gate structure or the like, dissimilarly to the prior art.
According to a sixth aspect of the present invention, a coupling coefficient measuring apparatus for a semiconductor memory having a first gate electrode and a second gate electrode coupled at a prescribed electrostatic coupling ratio with the first gate electrode and the second gate electrode serially arranged between a source region and a drain region comprises means setting the maximum voltage of the second gate electrode smaller than a voltage obtained by adding the threshold voltage of a second transistor having the second gate electrode as a gate and a drain voltage in a data area employed as a correct measured value when applying a prescribed voltage to the second gate voltage in a prescribed memory cell thereby applying a voltage to the first gate electrode by electrostatic coupling and measuring a first subthreshold current between the source region and the drain region, means directly applying a voltage to a test gate electrode in a test memory cell for measuring a second subthreshold current between the source region and the drain region, means measuring inclination of the first subthreshold current and inclination of the second subthreshold current, and means calculating the ratio between the inclination of the first subthreshold current and the inclination of the second subthreshold current thereby obtaining the coupling coefficient between the first gate electrode and the second gate electrode.
The coupling coefficient measuring apparatus for a semiconductor memory according to the sixth aspect sets the maximum voltage of the second gate electrode smaller than the voltage obtained by adding the threshold voltage of the second transistor having the second gate electrode as the gate and the drain voltage when measuring the first subthreshold current in a prescribed actual memory cell as hereinabove described, whereby the drain region of the second transistor can be prevented from supplying electrons to the drain of the first transistor having the first gate electrode as the gate. Therefore, the drain of the first transistor is held in sufficiently low electron concentration. Thus, the first subthreshold current flowing through the first transistor can be measured substantially in a range reflecting only fluctuation of electron concentration on the source of the first transistor. Consequently, the subthreshold current characteristics of only the first transistor can be correctly evaluated. The coupling coefficient between the first and second gate electrode can be correctly obtained by calculating the ratio between the inclination of the first subthreshold current measured in such a manner and inclination of the second subthreshold current measured by directly applying a voltage to the test gate electrode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.